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HI5767
Data Sheet February 2000 File Number 4319.4
10-Bit, 20/40/60 MSPS A/D Converter with Internal Voltage Reference
The HI5767 is a monolithic, 10-bit, analog-to-digital converter fabricated in a CMOS process. It is designed for high speed applications where wide bandwidth and low power consumption are essential. Its high sample clock rate is made possible by a fully differential pipelined architecture with both an internal sample and hold and internal band-gap voltage reference. The 250MHz Full Power Input Bandwidth and superior high frequency performance of the HI5767 converter make it an excellent choice for implementing Digital IF architectures in communications applications. The HI5767 has excellent dynamic performance while consuming only 310mW power at 40MSPS. Data output latches are provided which present valid data to the output bus with a latency of 7 clock cycles. The HI5767 is offered in 20MSPS, 40MSPS and 60MSPS sampling rates.
Features
* Sampling Rate . . . . . . . . . . . . . . . . . . . . . 20/40/60 MSPS * 8.8 Bits at fIN = 10MHz, fS = 40MSPS * Low Power at 40MSPS. . . . . . . . . . . . . . . . . . . . . .310mW * Wide Full Power Input Bandwidth. . . . . . . . . . . . . 250MHz * On-Chip Sample and Hold * Internal 2.5V Band-Gap Voltage Reference * Fully Differential or Single-Ended Analog Input * Single Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . +5V * TTL/CMOS Compatible Digital Inputs * CMOS Compatible Digital Outputs . . . . . . . . . . . 3.0V/5.0V * Offset Binary or Two's Complement Output Format
Applications
* Digital Communication Systems * QAM Demodulators * Professional Video Digitizing
Ordering Information
PART NUMBER HI5767/2CB HI5767/4CB HI5767/6CB HI5767/2CA HI5767/2IA HI5767/4CA HI5767/6CA HI5767EVAL1 HI5767EVAL2 TEMP. RANGE (oC) 0 to 70 0 to 70 0 to 70 0 to 70 PACKAGE 28 Ld SOIC 28 Ld SOIC 28 Ld SOIC 28 Ld SSOP PKG. NO. M28.3 M28.3 M28.3 M28.15 M28.15 M28.15 M28.15 SAMPLING RATE (MSPS) 20 40 60 20 20 40 60 60 60
* Medical Imaging * High Speed Data Acquisition
Pinout
HI5767 (SOIC, SSOP) TOP VIEW
DVCC1 1 DGND 2 DVCC1 3 DGND 4 AVCC 5 AGND 6 VREFIN 7 VREFOUT 8 VIN+ 9 VIN- 10 VDC 11 AGND 12 AVCC 13 OE 14 28 D0 27 D1 26 D2 25 D3 24 D4 23 DVCC2 22 CLK 21 DGND 20 D5 19 D6 18 D7 17 D8 16 D9 15 DFS
-40 to 85 28 LD SSOP 0 to 70 0 to 70 25 25 28 Ld SSOP 28 Ld SSOP
Evaluation Board Evaluation Board
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright (c) Intersil Corporation 2000
HI5767 Functional Block Diagram
VDC VINVIN+ S/H VREFOUT REFERENCE VREFIN BIAS CLOCK CLK
STAGE 1
DFS 2-BIT FLASH 2-BIT DAC OE
+
DVCC2
X2
D9 (MSB) D8 D7 D6 STAGE 8 DIGITAL DELAY AND DIGITAL ERROR CORRECTION D5 D4 D3 2-BIT FLASH 2-BIT DAC D2 D1 + D0 (LSB)
-
X2
DGND2
STAGE 9
2-BIT FLASH
AVCC
AGND
DVCC1
DGND1
2
HI5767 Typical Application Schematic
HI5767 VREFIN (7) VREFOUT (8) 0.1F (LSB) (28) D0 (27) D1 AGND (12) AGND (6) DGND1 (2) DGND1 (4) DGND2 (21) (26) D2 (25) D3 (24) D4 (20) D5 (19) D6 (18) D7 (17) D8 (MSB) (16) D9 VIN + VIN + (9) VDC (11) VIN VIN - (10) (1) DVCC1 (3) DVCC1 (23) DVCC2 0.1F CLOCK CLK (22) DFS (15) OE (14) (13) AVCC (5) AVCC 0.1F + 10F +5V D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 10F AND 0.1F CAPS ARE PLACED AS CLOSE TO PART AS POSSIBLE + 10F +5V DGND AGND BNC
Pin Descriptions
PIN NO. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 NAME DVCC1 DGND1 DVCC1 DGND1 AVCC AGND VREFIN VREFOUT VIN+ VINVDC AGND AVCC OE DESCRIPTION Digital Supply (+5.0V) Digital Ground Digital Supply (+5.0V) Digital Ground Analog Supply (+5.0V) Analog Ground +2.5V Reference Voltage Input +2.5V Reference Voltage Output Positive Analog Input Negative Analog Input DC Bias Voltage Output Analog Ground Analog Supply (+5.0V) Digital Output Enable Control Input PIN NO. 15 16 17 18 19 20 21 22 23 24 25 26 27 28 NAME DFS D9 D8 D7 D6 D5 DGND2 CLK DVCC2 D4 D3 D2 D1 D0 DESCRIPTION Data Format Select Input Data Bit 9 Output (MSB) Data Bit 8 Output Data Bit 7 Output Data Bit 6 Output Data Bit 5 Output Digital Ground Sample Clock Input Digital Output Supply (+3.0V or +5.0V) Data Bit 4 Output Data Bit 3 Output Data Bit 2 Output Data Bit 1 Output Data Bit 0 Output (LSB)
3
HI5767
Absolute Maximum Ratings TA = 25oC
Supply Voltage, AVCC or DVCC to AGND or DGND . . . . . . . . . . .6V DGND to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3V Digital I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DGND to DVCC Analog I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . AGND to AVCC
Thermal Information
Thermal Resistance (Typical, Note 1) JA (oC/W) SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 SSOP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . .150oC Maximum Storage Temperature Range . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC (SOIC - Lead Tips Only)
Operating Conditions
Temperature Range HI5767/xCx (Typ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to 70oC
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 1. JA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
AVCC = DVCC1 = 5.0V, DVCC2 = 3.0V; VREFIN = VREFOUT; fS = 40MSPS at 50% Duty Cycle; CL = 10pF; TA = 25oC; Differential Analog Input; Typical Values are Test Results at 25oC, Unless Otherwise Specified TEST CONDITIONS MIN TYP MAX UNITS
PARAMETER ACCURACY Resolution Integral Linearity Error, INL Differential Linearity Error, DNL (Guaranteed No Missing Codes) Offset Error, VOS Full Scale Error, FSE DYNAMIC CHARACTERISTICS Minimum Conversion Rate Maximum Conversion Rate HI5767/2 HI5767/4 HI5767/6 Effective Number of Bits, ENOB HI5767/2 HI5767/4 HI5767/6 Signal to Noise and Distortion Ratio, SINAD RMS Signal = ------------------------------------------------------------RMS Noise + Distortion HI5767/2 HI5767/4 HI5767/6 Signal to Noise Ratio, SNR RMS Signal = -----------------------------RMS Noise HI5767/2 HI5767/4 HI5767/6 Total Harmonic Distortion, THD HI5767/2 HI5767/4
10 fIN = 1MHz Sinewave fIN = 1MHz Sinewave fIN = DC fIN = DC -40 -
0.75 0.35 4
1.75 1.0 40 -
Bits LSB LSB LSB LSB
No Missing Codes
-
0.5
1
MSPS
No Missing Codes No Missing Codes No Missing Codes
20 40 60
-
-
MSPS MSPS MSPS
fS = 20MSPS, fIN = 10MHz fS = 40MSPS, fIN = 10MHz fS = 60MSPS, fIN = 10MHz
8.7 8.55 8.1
9 8.8 8.4
-
Bits Bits Bits
fS = 20MSPS, fIN = 10MHz fS = 40MSPS, fIN = 10MHz fS = 60MSPS, fIN = 10MHz
-
55.9 54.7 53.8
-
dB dB dB
fS = 20MSPS, fIN = 10MHz fS = 40MSPS, fIN = 10MHz fS = 60MSPS, fIN = 10MHz fS = 20MSPS, fIN = 10MHz fS = 40MSPS, fIN = 10MHz
-
55.9 55 54
-
dB dB dB
-
-71 -65
-
dBc dBc
4
HI5767
Electrical Specifications
AVCC = DVCC1 = 5.0V, DVCC2 = 3.0V; VREFIN = VREFOUT; fS = 40MSPS at 50% Duty Cycle; CL = 10pF; TA = 25oC; Differential Analog Input; Typical Values are Test Results at 25oC, Unless Otherwise Specified (Continued) TEST CONDITIONS fS = 60MSPS, fIN = 10MHz fS = 20MSPS, fIN = 10MHz fS = 40MSPS, fIN = 10MHz fS = 60MSPS, fIN = 10MHz fS = 20MSPS, fIN = 10MHz fS = 40MSPS, fIN = 10MHz fS = 60MSPS, fIN = 10MHz fS = 20MSPS, fIN = 10MHz fS = 40MSPS, fIN = 10MHz fS = 60MSPS, fIN = 10MHz f1 = 1MHz, f2 = 1.02MHz fS = 17.72MHz, 6 Step, Mod Ramp fS = 17.72MHz, 6 Step, Mod Ramp (Note 2) 0.2V Overdrive (Note 2) MIN TYP -64.5 MAX UNITS dBc
PARAMETER HI5767/6 2nd Harmonic Distortion HI5767/2 HI5767/4 HI5767/6 3rd Harmonic Distortion HI5767/2 HI5767/4 HI5767/6 Spurious Free Dynamic Range, SFDR HI5767/2 HI5767/4 HI5767/6 Intermodulation Distortion, IMD Differential Gain Error Differential Phase Error Transient Response Over-Voltage Recovery ANALOG INPUT Maximum Peak-to-Peak Differential Analog Input Range (VIN+ - VIN-) Maximum Peak-to-Peak Single-Ended Analog Input Range Analog Input Resistance, RIN Analog Input Capacitance, CIN Analog Input Bias Current, IB+ or IBDifferential Analog Input Bias Current IBDIFF = (IB+ - IB-) Full Power Input Bandwidth, FPBW Analog Input Common Mode Voltage Range (VIN+ + VIN-) / 2 INTERNAL REFERENCE VOLTAGE Reference Voltage Output, VREFOUT (Loaded) Reference Output Current, IREFOUT Reference Temperature Coefficient REFERENCE VOLTAGE INPUT Reference Voltage Input, VREFIN Total Reference Resistance, RREFIN Reference Input Current, IREFIN DC BIAS VOLTAGE DC Bias Voltage Output, VDC Maximum Output Current (Note 3) (Note 3) (Note 3)
-
-76 -73 -70
-
dBc dBc dBc
-
-80 -69 -67
-
dBc dBc dBc
-
76 69 67 64 0.5 0.2 1 1
-
dBc dBc dBc dBc % Degree Cycle Cycle
-10 Differential Mode (Note 2) 0.25
0.5 1.0 1 10 0.5 250 -
+10 4.75
V V M pF A A MHz V
-
2.5 1 120
2 -
V mA ppm/oC
-
2.5 2.5 1
-
V k mA
-
3.0 -
0.2
V mA
5
HI5767
Electrical Specifications
AVCC = DVCC1 = 5.0V, DVCC2 = 3.0V; VREFIN = VREFOUT; fS = 40MSPS at 50% Duty Cycle; CL = 10pF; TA = 25oC; Differential Analog Input; Typical Values are Test Results at 25oC, Unless Otherwise Specified (Continued) TEST CONDITIONS MIN TYP MAX UNITS
PARAMETER DIGITAL INPUTS Input Logic High Voltage, VIH Input Logic Low Voltage, VIL Input Logic High Current, IIH Input Logic Low Current, IIL Input Capacitance, CIN DIGITAL OUTPUTS Output Logic High Voltage, VOH Output Logic Low Voltage, VOL Output Three-State Leakage Current, IOZ Output Logic High Voltage, VOH Output Logic Low Voltage, VOL Output Three-State Leakage Current, IOZ Output Capacitance, COUT TIMING CHARACTERISTICS Aperture Delay, tAP Aperture Jitter, tAJ Data Output Hold, tH Data Output Delay, tOD Data Output Enable Time, tEN Data Output Enable Time, tDIS Data Latency, tLAT Power-Up Initialization Sample Clock Pulse Width (Low) Sample Clock Pulse Width (High) Sample Clock Duty Cycle Variation POWER SUPPLY CHARACTERISTICS Analog Supply Voltage, AVCC Digital Supply Voltage, DVCC1 Digital Output Supply Voltage, DVCC2 At 3.0V At 5.0V Supply Current, ICC Power Dissipation Offset Error Sensitivity, VOS Gain Error Sensitivity, FSE NOTES:
CLK, DFS, OE CLK, DFS, OE CLK, DFS, OE, VIH = 5V CLK, DFS, OE, VIL = 0V
2.0 -10.0 -10.0 -
7
0.8 +10.0 +10.0 -
V V A A pF
IOH = 100A; DVCC2 = 5V IOL = 100A; DVCC2 = 5V VO = 0/5V; DVCC2 = 5V IOH = 100A; DVCC2 = 3V IOL = 100A; DVCC2 = 3V VO = 0/5V; DVCC2 = 3V
4.0 -10 2.4 -10 -
1 1 10
0.8 10 0.5 10 -
V V A V V A pF
For a Valid Sample (Note 2) Data Invalid Time (Note 2) fS = 40MSPS fS = 40MSPS fS = 40MSPS 11.3 11.3 -
5 5 5 6 5 5 12.5 12.5 5
7 20 -
ns psRMS ns ns ns ns Cycles Cycles ns ns %
4.75 4.75 2.7 4.75 -
5.0 5.0 3.0 5.0 62 310 0.7 0.1
5.25 5.25 3.3 5.25 -
V V V V mA mW LSB LSB
fIN = 1MHz and DFS = "0" fIN = 1MHz and DFS = "0" AVCC or DVCC = 5V 5% AVCC or DVCC = 5V 5%
2. Parameter guaranteed by design or characterization and not production tested. 3. With the clock low and DC input.
6
HI5767 Timing Waveforms
ANALOG INPUT tAP tAJ CLOCK INPUT 1.5V 1.5V tOD tH DATA OUTPUT 2.4V DATA N-1 DATA N 0.5V
FIGURE 1. INPUT TO OUTPUT TIMING
Typical Performance Curves
9.5 fIN = 1MHz 59 60
9.0 8.5 fIN = 10MHz 8.0
fIN = 5MHz 55 53 SINAD (dB) SNR (dB) 50
fIN = 1MHz
fIN = 5MHz
ENOB (BITS)
fIN = 15MHz 7.5 7.0 TA = 25oC 6.5 10 20 30 40 50 60 70 41 80 47
fIN = 10MHz 45 fIN = 15MHz TA = 25oC 40 10 20 30 40 50 60 70 80
SAMPLING FREQUENCY (MSPS)
SAMPLING FREQUENCY (MSPS)
FIGURE 2. EFFECTIVE NUMBER OF BITS (ENOB) AND SINAD vs SAMPLING FREQUENCY
FIGURE 3. SNR vs SAMPLING FREQUENCY
80 75 fIN = 1MHz 70 SFDR (dBc) -THD (dBc) 65 60 55 TA = 25oC 50 10 20 30 40 fIN = 5MHz
80 75
fIN = 1MHz
fIN = 5MHz 70 fIN = 15MHz 65 60 55 TA = 25oC 50 10 fIN = 10MHz
fIN = 10MHz fIN = 15MHz
50
60
70
80
20
30
40
50
60
70
80
SAMPLING FREQUENCY (MSPS)
SAMPLING FREQUENCY (MSPS)
FIGURE 4. -THD vs SAMPLING FREQUENCY
FIGURE 5. SFDR vs SAMPLING FREQUENCY
7
HI5767 Typical Performance Curves
9.5 9.0 8.5 ENOB (BITS) 8.0 60MSPS 7.5 7.0 6.5 6.0 5.5 30 TA = 25oC, fIN = 10MHz 35 40 45 50 55 60 65 70 20MSPS 40MSPS ENOB (BITS)
(Continued)
9.1 9.0 8.9 8.8 8.7 8.6 40MSPS 8.5 8.4 60MSPS TA = 25oC, fIN = 10MHz DIFFERENTIAL ANALOG INPUT 20MSPS
8.3 0.25 0.75
1.25
1.75
2.25
2.75
3.25
3.75
4.25
4.75
DUTY CYCLE (%, tH/tCLK)
VCM (V)
FIGURE 6. EFFECTIVE NUMBER OF BITS (ENOB) vs SAMPLE CLOCK DUTY CYCLE
FIGURE 7. EFFECTIVE NUMBER OF BITS (ENOB) vs ANALOG INPUT COMMON MODE VOLTAGE
80 70 SUPPLY CURRENT (mA) 60 ENOB (BITS) 50 40 30 20 10 DICC2 0 10 15 20 25 30 35 fS (MSPS) 40 45 50 55 60 DICC1 TA = 25oC, 1MHz < fIN < 15MHz AICC ICC
9.2 20MSPS 9.0 8.8 8.6 8.4 60MSPS 8.2 8.0 -40 fIN = 10MHz, VREFIN = VREFOUT DIFFERENTIAL ANALOG INPUT -20 0 20 40 60 80
40MSPS
TEMPERATURE (oC)
FIGURE 8. SUPPLY CURRENT vs SAMPLE CLOCK FREQUENCY
FIGURE 9. EFFECTIVE NUMBER OF BITS (ENOB) vs TEMPERATURE
2.530 REFERENCE VOLTAGE, (VREFOUT) (V)
3.1
2.525 VREFOUT 2.520 VDC (V) 3.0 VDC
2.515
2.510 -40
-20
0
20
40
60
80
2.9 -40
-20
0
20
40
60
80
TEMPERATURE (oC)
TEMPERATURE (oC)
FIGURE 10. INTERNAL REFERENCE VOLTAGE (VREFOUT) vs TEMPERATURE
FIGURE 11. DC BIAS VOLTAGE (VDC) vs TEMPERATURE
8
HI5767 Typical Performance Curves
6.5
(Continued)
80 70 ICC
6.0 tOD tOD (ns) 5.5
SUPPLY CURRENT (mA)
60 50 40 30 DICC1 20 10 DICC2 -20 0 20 40 60 80 AICC 60MSPS, fIN = 10MHz, AVCC = DVCC1 = 5V DVCC2 = 3V
5.0
4.5 -40
-20
0
20
40
60
80
0 -40
TEMPERATURE (oC)
TEMPERATURE (oC)
FIGURE 12. DATA OUTPUT DELAY (tOD) vs TEMPERATURE
FIGURE 13. SUPPLY CURRENT vs TEMPERATURE
0 -10 -20 OUTPUT LEVEL (dB) -30 -40 -50 -60 -70 -80 -90 -100 0 100 200 300 400 500 600 700 800 900 1023 FREQUENCY (BIN) VINTA = 25oC, fS = 60MSPS, fIN = 10MHz VIN+
1 1 2 1
CS CS
CH
1
VOUT+ VOUT-
-+
+-
1
CH
1
FIGURE 14. 2048 POINT FFT PLOT
FIGURE 15. ANALOG INPUT SAMPLE-AND-HOLD
9
HI5767
TABLE 1. A/D CODE TABLE OFFSET BINARY OUTPUT CODE (DFS LOW) M S B D9 1 1 1 0 0 0 D8 1 1 0 1 0 0 D7 1 1 0 1 0 0 D6 1 1 0 1 0 0 D5 1 1 0 1 0 0 D4 1 1 0 1 0 0 D3 1 1 0 1 0 0 D2 1 1 0 1 0 0 D1 1 1 0 1 0 0 L S B D0 1 0 0 1 1 0 M S B D9 0 0 0 1 1 1 D8 1 1 0 1 0 0 D7 1 1 0 1 0 0 D6 1 1 0 1 0 0 D5 1 1 0 1 0 0 D4 1 1 0 1 0 0 D3 1 1 0 1 0 0 D2 1 1 0 1 0 0 D1 1 1 0 1 0 0 TWO'S COMPLEMENT OUTPUT CODE (DFS HIGH) L S B D0 1 0 0 1 1 0
CODE CENTER DESCRIPTION +Full Scale (+FS) 1/ LSB 4 +FS - 11/4 LSB +3/4 LSB -1/4 LSB -FS + 13/4 LSB -Full Scale (-FS) + 3/ LSB 4 NOTE:
DIFFERENTIAL INPUT VOLTAGE (VIN+ - VIN-) 0.499756V 0.498779V 732.422V -244.141V -0.498291V -0.499268V
4. The voltages listed above represent the ideal center of each output code shown with VREFIN = +2.5V.
Detailed Description
Theory of Operation
The HI5767 is a 10-bit fully differential sampling pipeline A/D converter with digital error correction logic. Figure 16 depicts the circuit for the front end differential-in-differential-out sampleand-hold (S/H). The switches are controlled by an internal sampling clock which is a non-overlapping two phase signal, 1 and 2 , derived from the master sampling clock. During the sampling phase, 1 , the input signal is applied to the sampling capacitors, CS. At the same time the holding capacitors, CH , are discharged to analog ground. At the falling edge of 1 the input signal is sampled on the bottom plates of the sampling capacitors. In the next clock phase, 2 , the two bottom plates of the sampling capacitors are connected together and the holding capacitors are switched to the op-amp output nodes. The charge then redistributes between CS and CH completing one sample-and-hold cycle. The front end sample-and-hold output is a fully-differential, sampled-data representation of the analog input. The circuit not only performs the sample-and-hold function but will also convert a single-ended input to a fullydifferential output for the converter core. During the sampling phase, the VIN pins see only the on-resistance of a switch and CS. The relatively small values of these components result in a typical full power input bandwidth of 250MHz for the converter. As illustrated in the functional block diagram and the timing diagram in Figure 1, eight identical pipeline subconverter stages, each containing a two-bit flash converter and a twobit multiplying digital-to-analog converter, follow the S/H circuit with the ninth stage being a two bit flash converter. Each converter stage in the pipeline will be sampling in one phase and amplifying in the other clock phase. Each individual subconverter clock signal is offset by 180 degrees from the previous stage clock signal resulting in alternate stages in the pipeline performing the same operation.
The output of each of the eight identical two-bit subconverter stages is a two-bit digital word containing a supplementary bit to be used by the digital error correction logic. The output of each subconverter stage is input to a digital delay line which is controlled by the internal sampling clock. The function of the digital delay line is to time align the digital outputs of the eight identical two-bit subconverter stages with the corresponding output of the ninth stage flash converter before applying the eighteen bit result to the digital error correction logic. The digital error correction logic uses the supplementary bits to correct any error that may exist before generating the final ten bit digital data output of the converter. Because of the pipeline nature of this converter, the digital data representing an analog input sample is output to the digital data bus on the 7th cycle of the clock after the analog sample is taken. This time delay is specified as the data latency. After the data latency time, the digital data representing each succeeding analog sample is output during the following clock cycle. The digital output data is synchronized to the external sampling clock by a double buffered latching technique. The digital output data is available in two's complement or offset binary format depending on the state of the Data Format Select (DFS) control input (see Table 1, A/D Code Table).
Internal Reference Voltage Output, VREFOUT
The HI5767 is equipped with an internal reference voltage generator, therefore, no external reference voltage is required. VREFOUT must be connected to VREFIN when using the internal reference voltage. An internal band-gap reference voltage followed by an amplifier/buffer generates the precision +2.5V reference voltage used by the converter. A 4:1 array of substrate PNPs generates the "delta-VBE" and a two-stage op-amp closes the loop to create an internal +1.25V band-gap reference voltage. This voltage is then amplified by a wideband uncompensated operational amplifier connected
10
HI5767
in a gain-of-two configuration. An external, user-supplied, 0.1F capacitor connected from the VREFOUT output pin to analog ground is used to set the dominant pole and to maintain the stability of the operational amplifier. the VIN and -VIN input signals are 0.5VP-P, with -VIN being 180 degrees out of phase with VIN . The converter will be at positive full scale when the VIN+ input is at VDC + 0.25V and the VIN- input is at VDC - 0.25V (VIN+ - VIN- = +0.5V). Conversely, the converter will be at negative full scale when the VIN+ input is equal to VDC - 0.25V and VIN- is at VDC + 0.25V (VIN+ - VIN- = -0.5V). The analog input can be DC coupled (Figure 18) as long as the inputs are within the analog input common mode voltage range (0.25V VDC 4.75V).
VIN VDC R C VIN+ HI5767 VDC
Reference Voltage Input, VREFIN The HI5767 is designed to accept a +2.5V reference voltage source at the VREFIN input pin. Typical operation of the converter requires VREFIN to be set at +2.5V. The HI5767 is tested with VREFIN connected to VREFOUT yielding a fully differential analog input voltage range of 0.5V.
The user does have the option of supplying an external +2.5V reference voltage. As a result of the high input impedance presented at the VREFIN input pin, 2.5k typically, the external reference voltage being used is only required to source 1mA of reference input current. In the situation where an external reference voltage will be used an external 0.1F capacitor must be connected from the VREFOUT output pin to analog ground in order to maintain the stability of the internal operational amplifier. In order to minimize overall converter noise it is recommended that adequate high frequency decoupling be provided at the reference voltage input pin, VREFIN .
-VIN
VDC
R VIN-
FIGURE 17. DC COUPLED DIFFERENTIAL INPUT
Analog Input, Differential Connection
The analog input to the HI5767 is a differential input that can be configured in various ways depending on the signal source and the required level of performance. A fully differential connection (Figure 17 and Figure 18) will deliver the best performance from the converter.
VIN R VIN+ HI5767 VDC R
The resistors, R, in Figure 18 are not absolutely necessary but may be used as load setting resistors. A capacitor, C, connected from VIN+ to VIN- will help filter any high frequency noise on the inputs, also improving performance. Values around 20pF are sufficient and can be used on AC coupled inputs as well. Note, however, that the value of capacitor C chosen must take into account the highest frequency component of the analog input signal.
Analog Input, Single-Ended Connection
The configuration shown in Figure 19 may be used with a single ended AC coupled input.
VIN R VDC HI5767 VINVIN+
-VIN
VIN-
FIGURE 16. AC COUPLED DIFFERENTIAL INPUT
Since the HI5767 is powered by a single +5V analog supply, the analog input is limited to be between ground and +5V. For the differential input connection this implies the analog input common mode voltage can range from 0.25V to 4.75V. The performance of the ADC does not change significantly with the value of the analog input common mode voltage. A DC voltage source, VDC , equal to 3.2V (typical), is made available to the user to help simplify circuit design when using an AC coupled differential input. This low output impedance voltage source is not designed to be a reference but makes an excellent DC bias source and stays well within the analog input common mode voltage range over temperature. For the AC coupled differential input (Figure 17) and with VREFIN connected to VREFOUT, full scale is achieved when 11
FIGURE 18. AC COUPLED SINGLE ENDED INPUT
Again, with VREFIN connected to VREFOUT, if VIN is a 1VP-P sinewave, then VIN+ is a 1.0VP-P sinewave riding on a positive voltage equal to VDC. The converter will be at positive full scale when VIN+ is at VDC + 0.5V (VIN+ - VIN- = +0.5V) and will be at negative full scale when VIN+ is equal to VDC - 0.5V (VIN+ - VIN= -0.5V). Sufficient headroom must be provided such that the input voltage never goes above +5V or below AGND. In this case, VDC could range between 0.5V and 4.5V without a significant change in ADC performance. The simplest way to produce VDC is to use the DC bias source, VDC, output of the HI5767. The single ended analog input can be DC coupled (Figure 20) as long as the input is within the analog input common mode voltage range.
HI5767
VIN VDC R C VDC HI5767 VINVIN+
The part should be mounted on a board that provides separate low impedance connections for the analog and digital supplies and grounds. For best performance, the supplies to the HI5767 should be driven by clean, linear regulated supplies. The board should also have good high frequency decoupling capacitors mounted as close as possible to the converter. If the part is powered off a single supply, then the analog supply should be isolated with a ferrite bead from the digital supply. Refer to the application note "Using Intersil High Speed A/D Converters" (AN9214) for additional considerations when using high speed converters.
FIGURE 19. DC COUPLED SINGLE ENDED INPUT
The resistor, R, in Figure 20 is not absolutely necessary but may be used as a load setting resistor. A capacitor, C, connected from VIN+ to VIN- will help filter any high frequency noise on the inputs, also improving performance. Values around 20pF are sufficient and can be used on AC coupled inputs as well. Note, however, that the value of capacitor C chosen must take into account the highest frequency component of the analog input signal. A single ended source may give better overall system performance if it is first converted to differential before driving the HI5767.
Static Performance Definitions
Offset Error (VOS)
The midscale code transition should occur at a level 1/4 LSB above half-scale. Offset is defined as the deviation of the actual code transition from this point.
Full-Scale Error (FSE)
The last code transition should occur for an analog input that is 3/4 LSB below Positive Full Scale (+FS) with the offset error removed. Full scale error is defined as the deviation of the actual code transition from this point.
Digital Output Control and Clock Requirements
The HI5767 provides a standard high-speed interface to external TTL logic families. In order to ensure rated performance of the HI5767, the duty cycle of the clock should be held at 50% 5%. It must also have low jitter and operate at standard TTL levels. Performance of the HI5767 will only be guaranteed at conversion rates above 1 MSPS. This ensures proper performance of the internal dynamic circuits. Similarly, when power is first applied to the converter, a maximum of 20 cycles at a sample rate above 1 MSPS will have to be performed before valid data is available.A Data Format Select (DFS) pin is provided which will determine the format of the digital data outputs. When at logic low, the data will be output in offset binary format. When at logic high, the data will be output in two's complement format. Refer to Table 1 for further information. The output enable pin, OE, when pulled high will three-state the digital outputs to a high impedance state. Set the OE input to logic low for normal operation.
OE INPUT 0 1 DIGITAL DATA OUTPUTS Active High Impedance
Differential Linearity Error (DNL)
DNL is the worst case deviation of a code width from the ideal value of 1 LSB.
Integral Linearity Error (INL)
INL is the worst case deviation of a code center from a best fit straight line calculated from the measured data.
Power Supply Sensitivity
Each of the power supplies are moved plus and minus 5% and the shift in the offset and full scale error (in LSBs) is noted.
Dynamic Performance Definitions
Fast Fourier Transform (FFT) techniques are used to evaluate the dynamic performance of the HI5767. A low distortion sine wave is applied to the input, it is coherently sampled, and the output is stored in RAM. The data is then transformed into the frequency domain with an FFT and analyzed to evaluate the dynamic performance of the A/D. The sine wave input to the part is typically -0.5dB down from full scale for all these tests. SNR and SINAD are quoted in dB. The distortion numbers are quoted in dBc (decibels with respect to carrier) and DO NOT include any correction factors for normalizing to full scale. The Effective Number of Bits (ENOB) is calculated from the SINAD data by: ENOB = (SINAD - 1.76 + VCORR) / 6.02, where: VCORR = 0.5 dB (Typical).
Supply and Ground Considerations
The HI5767 has separate analog and digital supply and ground pins to keep digital noise out of the analog signal path. The digital data outputs also have a separate supply pin, DVCC2 , which can be powered from a 3.0V or 5.0V supply. This allows the outputs to interface with 3.0V logic if so desired.
VCORR adjusts the SINAD, and hence the ENOB, for the amount the analog input signal is backed off from full scale.
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HI5767
Signal To Noise and Distortion Ratio (SINAD)
SINAD is the ratio of the measured RMS signal to RMS sum of all the other spectral components below the Nyquist frequency, fS/2, excluding DC.
Video Definitions
Differential Gain and Differential Phase are two commonly found video specifications for characterizing the distortion of a chrominance signal as it is offset through the input voltage range of an ADC.
Signal To Noise Ratio (SNR)
SNR is the ratio of the measured RMS signal to RMS noise at a specified input and sampling frequency. The noise is the RMS sum of all of the spectral components below fS /2 excluding the fundamental, the first five harmonics and DC.
Differential Gain (DG)
Differential Gain is the peak difference in chrominance amplitude (in percent) relative to the reference burst.
Differential Phase (DP)
Differential Phase is the peak difference in chrominance phase (in degrees) relative to the reference burst.
Total Harmonic Distortion (THD)
THD is the ratio of the RMS sum of the first 5 harmonic components to the RMS value of the fundamental input signal.
2nd and 3rd Harmonic Distortion
This is the ratio of the RMS value of the applicable harmonic component to the RMS value of the fundamental input signal.
Timing Definitions
Refer to Figure 1 and Figure 2 for these definitions.
Aperture Delay (tAP)
Aperture delay is the time delay between the external sample command (the falling edge of the clock) and the time at which the signal is actually sampled. This delay is due to internal clock path propagation delays.
Spurious Free Dynamic Range (SFDR)
SFDR is the ratio of the fundamental RMS amplitude to the RMS amplitude of the next largest spectral component in the spectrum below fS /2.
Intermodulation Distortion (IMD)
Nonlinearities in the signal path will tend to generate intermodulation products when two tones, f1 and f2 , are present at the inputs. The ratio of the measured signal to the distortion terms is calculated. The terms included in the calculation are (f1+f2), (f1-f2), (2f1), (2f2), (2f1+f2), (2f1-f2), (f1+2f2), (f1-2f2). The ADC is tested with each tone 6dB below full scale.
Aperture Jitter (tAJ)
Aperture jitter is the RMS variation in the aperture delay due to variation of internal clock path delays.
Data Hold Time (tH)
Data hold time is the time to where the previous data (N - 1) is no longer valid.
Data Output Delay Time (tOD)
Data output delay time is the time to where the new data (N) is valid.
Transient Response
Transient response is measured by providing a full-scale transition to the analog input of the ADC and measuring the number of cycles it takes for the output code to settle within 10-bit accuracy.
Data Latency (tLAT)
After the analog sample is taken, the digital data representing an analog input sample is output to the digital data bus on the 7th cycle of the clock after the analog sample is taken. This is due to the pipeline nature of the converter where the analog sample has to ripple through the internal subconverter stages. This delay is specified as the data latency. After the data latency time, the digital data representing each succeeding analog sample is output during the following clock cycle. The digital data lags the analog input sample by 7 sample clock cycles.
Over-Voltage Recovery
Over-Voltage Recovery is measured by providing a full-scale transition to the analog input of the ADC which overdrives the input by 200mV, and measuring the number of cycles it takes for the output code to settle within 10-bit accuracy.
Full Power Input Bandwidth (FPBW)
Full power input bandwidth is the analog input frequency at which the amplitude of the digitally reconstructed output has decreased 3dB below the amplitude of the input sine wave. The input sine wave has an amplitude which swings from -FS to +FS. The bandwidth given is measured at the specified sampling frequency.
Power-Up Initialization
This time is defined as the maximum number of clock cycles that are required to initialize the converter at power-up. The requirement arises from the need to initialize the dynamic circuits within the converter.
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site www.intersil.com 13

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